The present invention relates to a semiconductor fabrication technology, and more particularly, to a method of fabricating a transistor for use in a semiconductor device.
As semiconductor devices are being highly integrated, one of important issues is to fabricate transistors that can ensure a high current drivability and a short channel margin even at small dimensions.
Recently, extensive studies have been conducted to increase carrier mobility in order to ensure a high current drivability. Carrier mobility may be increased by applying a certain stress to a channel region defined under a gate, leading to improving current characteristic of transistors. To this end, various transistor structures and fabrication methods thereof have been proposed, and one such example is illustrated in FIGS. 1A to 1D.
FIGS. 1A to 1D are cross-sectional views explaining a structure of a conventional PMOS transistor and a fabrication method thereof.
Referring to FIG. 1A, a device isolation layer 11 is formed on a substrate 10 to define an active region.
A gate pattern 12 having a stacked structure of a gate insulation layer, a gate electrode and a gate hard mask is formed on the substrate 10, and a gate spacer 13 is formed on a sidewall of the gate pattern 12.
Referring to FIG. 1B, the substrate 10 on either side of the gate spacer 13 is etched to a certain depth to form a trench T. Reference numeral 11A represents an etched device isolation layer.
Referring to FIG. 1C, an epitaxial layer 14 is grown within the trench T by using a sidewall and/or bottom of the trench T as a seed layer.
The epitaxial layer 14 is used to apply a stress to the channel region of the substrate 10. In the case of the PMOS transistor, a compression stress is applied in a direction parallel to the channel region in order to increase the mobility of majority carriers, i.e., holes. Thus, the epitaxial layer 14 is formed of a material having a larger lattice constant than the substrate 10. For example, when the substrate 10 is a Si substrate, the epitaxial layer 14 may be a SiGe epitaxial layer.
Referring to FIG. 1D, an initial source/drain region 15 is formed by ion implantation of P-type dopants such as boron (B).
Referring to FIG. 1E, a thermal treatment is performed for dopant activation. As a result, the dopants are diffused to form a final source/drain region 15A. In this manner, a PMOS transistor having a structure of FIG. 1E is completed.
However, there are the following limitations on the structure of the conventional PMOS transistor and the fabrication method thereof.
When the epitaxial layer 14 such as SiGe is grown, it is grown not uniformly but in a convex shape (see FIGS. 1C to 1E). Due to the shape of the epitaxial layer 14, the dopants for forming the source/drain region in a subsequent process are relatively more ion-implanted into edges of the gate pattern 12 than other positions (see FIG. 1D). From the profile of the final source/drain region 15A when the dopants are diffused by the subsequent thermal treatment, it can be seen that lateral diffusion of the dopants is so active that the side of the final source/drain region 15A penetrates even under the gate pattern 12, whereas the bottom of the final source/drain region 15A is relatively shallow.
If the side of the final source/drain region 15A penetrates even under the gate pattern 12, the short channel margin of the transistor is degraded and, in particular, Drain Induced Barrier Lowering (DIBL) is degraded.
Furthermore, if the bottom of the final source/drain region 15A is shallow, leakage current characteristic is degraded due to interface defect between the substrate 10 and the epitaxial layer 14.
Therefore, there is a need for a method of fabricating a new transistor capable of solving the above-mentioned limitations.